1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for preventing short-circuits between semiconductor layers and between a data line and the gate line.
2. Discussion of the Related Art
Generally, liquid crystal display devices control the light transmittance of liquid crystals by using an electric field to display a picture. To this end, the liquid crystal display device includes a liquid crystal display panel with liquid crystal cells arranged in a matrix form, and a driving circuit to drive the liquid crystal display panel. Pixel electrodes and common electrodes are provided to apply an electric field to each of the liquid crystal cells. Normally, the pixel electrode is formed on a lower substrate by liquid crystal cells, whereas the common electrode is integrated into the entire surface of an upper substrate. Each pixel electrode is connected to a thin film transistor (hereinafter, referred to as a TFT) used as a switching device. The pixel electrode drives the liquid crystal cell along with the common electrode in accordance with data signals applied through the thin film transistor.
The lower substrate of the liquid crystal display device requires a plurality of mask processes as well as a semiconductor process, thus the fabricating process becomes complicated and acts as a major factor for increasing the fabricating cost of the liquid crystal display panel. Accordingly, the lower substrate has been developed in a direction of reducing the number of mask processes. This is because one mask process includes several processes such as a deposition process, a cleaning process, a photolithography process, an etching process, an exfoliation process, and a testing process. Accordingly, a four-mask process has recently been on the rise, wherein one of the process steps from a five-mask process has been omitted.
FIGS. 1 and 2 are a plane view and a cross-sectional view illustrating a lower substrate formed by a four-mask process.
Referring to both FIGS. 1 and 2, a lower substrate 1 of the liquid crystal display device includes a TFT 30 located at each intersection of a plurality of data lines 4 and gate lines 2, and a pixel electrode 22 connected to the drain electrode 10 of the TFT 30.
The TFT 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22 through a drain contact hole 20.
The gate electrode 6 overlaps a portion of the data line 4. The drain electrode 10 has a neck part 10a where the drain electrode 10 overlaps the gate electrode 6, and a head part 10b where the drain electrode 10 overlaps the pixel electrode 22. The source electrode 8 is formed to face into the neck part 10a of the drain electrode 10 having a U-shaped channel therebetween.
The TFT 30 further includes semiconductor layers 14 and 16 to form a conductive channel between the source electrode 8 and the drain electrode 10 by applying a gate voltage to the gate electrode 6. The TFT 30 selectively supplies a data signal from the data line 4 to the pixel electrode 22 in response to a gate signal from the gate line 2.
The pixel electrode 22 is located at a cell area divided by the data line 4 and the gate line 2 and formed of a transparent conductive material having a high light transmittance. The pixel electrode 22 is formed on a protective layer 18 spread on the entire surface of the lower substrate 1, and is electrically connected to the drain electrode 10 through a drain contact hole 20 that penetrates the protective layer 18. A potential difference is generated between the pixel electrode 22 and a common transparent electrode (not shown) formed in the upper substrate (not shown) by the data signal supplied through the TFT 30. The potential difference causes the liquid crystals located between the lower substrate 1 and the upper substrate (not shown) to rotate due to the dielectric constant anisotropy. The rotating liquid crystals cause a light incident through the pixel electrode 22 from a light source to be transmitted to the upper substrate.
The method of fabricating the lower substrate of the liquid crystal display device will be described in conjunction with FIGS. 3A to 3D.
Referring to FIG. 3A, the gate electrode 6 and the gate line 2 are formed on the lower substrate 1.
To this end, a gate metal layer is deposited on the lower substrate 1 by a vapor deposition method, such as a sputtering method. The gate metal layer is formed of aluminum (Al) or aluminum alloy. The gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate electrode 6 and the gate line 2 on the lower substrate 1.
Referring to FIG. 3B, a gate insulating layer 12, an active layer 14, an ohmic contact layer 16, a data line 4, a source electrode 8, and a drain electrode 10 are formed on the lower substrate having the gate electrode 6 and the gate line 2 formed thereon.
To this end, the gate insulating layer 12, first and second semiconductor layers, and a data line metal layer are sequentially deposited by a vapor deposition method, such as chemical vapor deposition (CVD) or sputtering, on the lower substrate 1 having the gate electrode 6 and the gate line 2. Herein, the gate insulating layer 12 is formed of an inorganic insulating material, such as silicon oxide (SiOx) or silicon nitride (SiNx), a first semiconductor layer is formed of undoped amorphous silicon, a second semiconductor layer is formed of doped amorphous silicon, and the data line metal layer is formed of molybdenum (Mo) or molybdenum alloy.
A photoresist pattern is formed on the data line metal layer by a photolithography process using a second mask. In this case, a half-tone mask with a semi-transmitting part at the channel part of the TFT is used as a second mask, thus the photoresist pattern corresponding to a channel part is lower in height than the photoresist pattern corresponding to a source/drain electrode.
The data line metal layer is patterned by a wet etching process using the photoresist pattern, whereby the data line 4, the source electrode 8, and the drain electrode 10 are formed.
Then, the first and second semiconductors are simultaneously patterned by a dry etching process using the same photoresist pattern to form an active layer 14 and an ohmic contact layer 16.
And, the photoresist pattern having a low height at the channel is removed by an ashing process, and the data line metal layer and the ohmic contact layer formed at the channel part are etched by the dry etching process using the remaining photoresist pattern. Accordingly, the active layer 14 of the channel part is exposed to separate the source electrode 8 from the drain electrode 10.
Then, the remaining photoresist pattern is removed from the source electrode 8 and the drain electrode 10 by a strip process.
Referring to FIG. 3C, a protective layer 18 with a drain contact hole 20 on the gate insulating layer 12 where the source electrode 8, the drain electrode 10 and the data line are formed. The protective layer 18 is formed of an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiOx), or an organic insulating material, such as an acrylic organic compound, benzocyclobutene (BCB), and perfluorocyclobutane (PFCB). Subsequently, the protective layer 18 is patterned by a photolithography process and an etching process using a third mask to form the drain contact hole 20. The drain contact hole 20 is formed in the protective layer 18 to expose the drain electrode 10.
Referring to FIG. 3D, the pixel electrode 22 is formed on the protective layer 18. A transparent metal layer is formed on the lower substrate 1 where the protective layer 18 is formed by a vapor deposition method, such as a sputtering method. The transparent metal layer is formed of indium tin oxide (ITO), indium zinc oxide (IZO) or indium tin zinc oxide (ITZO). Subsequently, the transparent metal layer is patterned by a photolithography process and an etching process using a fourth mask to form the pixel electrode 22. The pixel electrode 22 is connected to the drain electrode 10 through the drain contact hole 20 that is formed in the protective layer 18.
In the liquid crystal display device, the data line metal layer and the semiconductor layer are patterned by the same mask to form the active layer 14, the ohmic contact layer 16, the data line 4, the source electrode 8, and the drain electrode 10. In this case, the channel part formed between the source and drain electrodes 8 and 10 are formed to overlap the gate electrode 6, thereby restraining an increase of an optical pumping current by the light incident from a backlight. However, there occasionally occurs a case that the optical pumping current increases within the active layer 14 formed at the end of the gate electrode 6, since the light incident from the backlight is not intercepted by the gate electrode 6. In order to resolve this problem, as shown at P1 area in FIG. 1, a trench is formed on the active layer 14 formed at the end of the gate electrode 6.
Nevertheless, a short-circuit is generated between active layers where the data line 4 and the drain electrode 10 are formed, so that the optical pumping current increases with the active layer.
More specifically, the data line 4 and the drain electrode 10 formed at the end of the projected parts of the gate electrode 6, as shown in FIG. 4, are formed with a specific gap d1 therebetween. The active layers 14a and 14b and the ohmic contact layer 16 formed at the lower part of the data line 4 and the drain electrode 10 are simultaneously formed with the same mask when forming the data line 4 and the drain electrode 10. In this case, the width of the active layers 14a and 14b is formed to be wider than that of the data line 4 and the drain electrode 10. Accordingly, the short circuit between the first and second active layers 14a and 14b often occurs by the pattern defect between the first active layer 14a formed at the lower part of the data line 4 and the second active layer 14b formed at the lower part of the drain electrode 10 in an area except the gate electrode. A bad channel formed between the data line 4 and the drain electrode 10 causes by short circuit is excited by the light incident from the backlight to increase the optical pumping current with the active layer 14. This is because charges existing in the active layer 14 react on the light to increase the optical pumping current. Thus, a voltage charged in the pixel electrode 22 is discharged to the data line 4 through the bad channel, thereby generating a brightness spot, since the voltage charged in the pixel electrode 22 becomes lower.
Further, as shown in FIG. 4, the distance between the data line 4 and the drain electrode is narrow, thus there often occurs a case that the data line 4 and the drain electrode 10 are shorted. In this case, the data signal may be applied to the pixel electrode 22 through the shorted data line 4 and the drain electrode 10 regardless of the gate signal.